Quad Anemone™ Floating Point Co-Processor VITA-57 FMC

Overview

The AA-FMC (AAFM) is a VITA-57 FPGA Mezzanine Card based on BittWare’s Anemone floating point co-processor for FPGAs. Featuring the Epiphany™ architecture from Adapteva, the Anemone allows users to combine the complex processing ability of a floating point C-programmable compute engine with the versatility and configurability of an FPGA to offer a completely new approach to floating point digital signal processing. Featuring four Anemone104 (AN104) processors, the AA-FMC adds 128 GFLOPS of total processing performance to BittWare’s Altera Stratix family of host boards.

Features

• Four BittWare Anemone104 co-processors for FPGA
• 128 GFLOPs of processing performance
• 64 independent floating point processor cores
• ANSI C-programmable
• IEEE floating point
• Shared memory architecture
• High-throughput mesh network for inter-core connectivity
• Off-board I/O via memory-mapped links
• Standard GNU/Eclipse development tools
• Air or conduction cooled

Specifications

The BittWare Anemone is a truly C-programmable floating point compute engine that achieves superior power efficiency and processing performance by working alongside an FPGA as a co-processor. The FPGA handles all the memory, I/O interfacing, protocol processing, and special functions, in addition to any computational tasks it may perform. This leaves the Anemone free to efficiently perform the complex processing tasks that DSPs are ideal for.

The first generation Anemone chip, the Anemone104 (AN104) is a completely scalable, up to 1 GHz multicore processor with 16 eCores that provide a total sustained performance of 32 GFLOPS while consuming only 2 Watts of total power. On-chip distributed shared memory is 4 Mb (32 KByte per eCore) with 32 GBytes/sec of sustained memory bandwidth within each eCore. The cache-less shared memory architecture is extended off-chip via external I/O links.

The AN104 features an internal high-throughput mesh network, with separate data paths for on-chip and off-chip communications. Total on-chip, inter-core bandwidth is 128 GBytes/sec full duplex, with an additional 8 GBytes/sec of off-chip bandwidth.

The AN104 provides a flexible low-overhead external interconnect scheme that supports memory-mapped direct connection of multiple AN104s and is compatible with any LVDS capable FPGA. This is achieved via four links that are full-duplex 8-bit LVDS data ports @ 500 MHz DDR, each simultaneously providing 1 GByte/sec in each direction for a total off-chip bandwidth of 8 GBytes/sec.

On the AAFM, the AN104s are arranged in a 2D mesh. All cores have direct memory mapped access to each other via the shared memory architecture and eMesh network. Link ports from two of the processors go to the FMC interface for memory and I/O connectivity via the FPGA on the host board.

Ordering Information

AAFM-RW-VXYZ

RW Ruggedisation Level:

• 0U = Commercial (0C to 50C)*
• 2C = Conduction cooled; 
conformal coating (-40C to 75C)*

V Anemone Processors:

• 1 = 1 AN104
• 2 = 2 AN104s
• 4 = 4 AN104s*

X AN104 Speed Grade:

• S = Slow
• F = Fast (1 GHz)
• T = Typical (900 MHz)*
• E = Engineering Sample

Y I2C Address:

• 1 = Default*

Z Assembly:

• F = Lead free assembly
• P = Lead based assembly*

* Default