XPedite6401 Now Available with NXP Arm-based QorIQ® Processors Integrating four 64-bit Arm® Cortex-A72 Cores
Extreme Engineering Solutions (X-ES) has announced added support for the NXP QorIQ LS1046A and LS1026A processors to XPedite6401 XMC/PMC mezzanine module.
The introduction of the NXP Arm® A72 core processors brings up to four 64-bit ARM Cortex-A72 cores to the XPedite6401, extending the available processor range and enabling support for a scalable low-power to high-performance embedded computing solution within a single product design.
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NXP Layerscape® LS1046A Processor Delivers High Power and Scalability
The XPedite6401 is an X-ES XMC/PrPMC mezzanine module that now supports an NXP LS1046A processor with up to four 64-bit Arm® Cortex-A72 cores with packet processing acceleration and high-speed peripherals. The LS1046A processor is the most powerful NXP Arm® core processor on the market to date, delivering best-in-class performance in excess of 32,000 CoreMarks®. It delivers excellent networking performance and flexible I/O options in a single System-on-Chip (SoC) design, making it well suited for embedded computing applications ranging from Small Form Factor (SFF) networking to security appliances.
The LS1046A processor is available in a 23 x 23 mm package and is pin-compatible with the LS1043A and LS1088A SoCs. This compatibility allows users to scale the performance of the XPedite6401 from between two to eight A53 cores all the way up to four A72 cores. With its high power-to-performance flexibility, the XPedite6401 can be easily tailored to specific project requirements and even be upgraded from a lower level processor to meet evolving computing needs.
The XPedite6401’s P16 connector provides access to an array of I/O from the processor, maximizing performance in a small package design. It supports up to two 10GBASE-KR Ethernet ports, two 1000BASE-X Ethernet ports or eight Ethernet ports through two QSGMII interfaces, one SATA port capable of 6 Gb/s, and one USB 3.0 port.
Security Features for Trusted Computing
NXP’s Trust Architecture is integrated into all Layerscape devices, including support for Secure Boot, memory access control/strong partitioning, persistent storage, security state monitoring, master secrets, security violation detection, and secure debug.
Secure Boot prevents inauthentic code from executing by verifying software against a device specific, one-time programmable master key while the processor remains in a secure state, thereby preventing data extraction. The features of NXP’s Trust Architecture expands the capabilities of XPedite6401 for high security applications.
X-ES offers a turn-key Secure Boot implementation package for all of our NXP Layerscape processor-based hardware. The Secure Boot package simplifies the code signing process for the customer, providing the NXP Code Signing Tool as well as a revised U-Boot bootloader adding the ability to validate
images that are signed for X-ES processor boards.
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