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A5-PCIe-L


Overview

Intel FPGA Board -  Arria® V FPGA GZ Low Profile PCIe Board with Dual QSFP+ and DDR3, QDRII+, or RLDRAM3

BittWare’s A5-PCIe-L (A5PL) is a low-profile PCIe x8 card based on the Altera Arria V GZ FPGA. The high-performance, power-efficient Arria V GZ FPGA provides a high level of system integration and flexibility for I/O, routing, and processing.

Technical

The A5PL FPGA board provides a variety of interfaces for high-speed serial I/O as well as debug support. Two QSFP+ cages are available on the front panel, each supporting 40GigE or four 10GigE channels using optical transceivers as well as passive copper cabling up to 8 meters. The QSFP+ cages can optionally be adapted for SFP+.

The Gen3 x8 PCIe interface provides 8 SerDes lanes to the Arria V GZ FPGA. A USB 2.0 interface and an optional JTAG connector are available for debug and programming support.

  • High performance Altera Arria V GZ FPGA
  • PCIe x8 interface supporting Gen1, Gen2, or Gen3
  • Dual QSFP+ cages for 2x 40GigE or 8x 10GigE
  • Board Management Controller for Intelligent Platform Management
  • USB 2.0 for programming and debug
  • Timestamping and synchronisation support

Specifications

FPGA

  • Intel Arria® V GZ FPGA
  • Up to 16 full-duplex, high-performance, multi-gigabit SerDes transceivers @ up to 12.5 GHz
  • Up to 450K logic elements available
  • Up to 34 Mb of embedded memory
  • 1.6 Gbps LVDS performance
  • Up to 2278 18×18 multipliers
 

On-Board Memory

  • Flash memory for booting FPGA
  •  

Optional SODIMM

  • DDR3: x72 w/ECC - Up to 8 GB
  • RLDRAM3: 2x banks of x18
  • - 2x (32 M x 18): 128 MB
  • - 2x (64 M x 18): 256 MB
  • - 2x (128 M x 18): 512 MB
  • QDRII+: 2x banks of x18 - 2x (8 M x 18): 36 MB
  •  

PCIe Interface

  • x8 Gen1, Gen2, Gen3 direct to FPGA
  •  

USB Header

  • USB 2.0 interface for debug and programming FPGA and Flash
  •  

Timestamp and Synchronization (Optional)

  • Tunable high-accuracy TCXO
  • Programmable clock synthesizer (Si5338)
  • 2 front panel SMA connectors*
    • 1 PPS input
    • Reference clock input
    •  

QSFP+ Cages

  • 2 QSFP+ cages on front panel connected to FPGA via 8 SerDes
  • Each supports 40GigE or 4 10GigE
  • Can be optionally adapted for use as SFP+
  •  

Baseboard Management Controller

  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 access
  • Voltage overrides
  •  

Size

  • Half-height, half-length (low profile) PCIe slot card
  • 168mm x 68.9mm
  • Max. component height: 14.47mm

Technical documents

Ordering information

There are a number of different configurations available. Please contact Sarsen Technology to discuss the options.