BittWare SP/S4-AMC Altera Stratix® IV GX AdvancedMC Board with four SFP/SFP+

FPGA-Computing AdvancedMC with SFP/SFP+ FPGA Mezzanine Card

BittWare's SP/S4-AMC (SP/S4AM)is a full-size, single wide AdvancedMC that can be attached to AdvancedTCA (Advanced Telecom Compute Architecture) carriers or other cards equipped with AMC bays, and used in MicroTCA systems. The BittWare S4AM features a high-density, low-power Altera Stratix IV GX FPGA designed specifically for serial I/O-based applications, creating a completely flexible, reconfigurable AMC.

BittWare’s Atlantis FrameWork, in conjunction with the FINe Host/Control Bridge, greatly simplifies application development and integration of this powerful Altera Stratix IV GX based board. Four small form-factor pluggable-plus (SFP/SFP+) compact optical transceiver connectors are available on the front panel. The board also provides an IPMI system management interface, a configurable 15 port AMC SerDes interface supporting a variety of protocols.

Additionally, the SP/S4-AMC features 10/100 Ethernet, Gigabit Ethernet, two banks of DDR3 SDRAM, two banks of QDRII+ SRAM, and Flash memory for booting the FPGAs and FINe.

SFP/SFP+ FPGA Mezzanine Card

The SP/S4AM provides a four-cage SFP/SFP+ connector on the front panel with each transceiver providing support for virtually any serial communication standard, including: Fibre Channel, Gigabit Ethernet, SONET, CPRI, and OBSAI. The four SFP/SFP+ SerDes channels are connected directly to the Stratix IV GX FPGA.

Altera Stratix IV GX FPGA

The Altera Stratix IV GX FPGA was specifically designed for serial I/O-based applications requiring high-density, reconfigurable logic. The Stratix IV GX provides 19 full-duplex, multi-gigabit transceivers, 16 of which are high-performance, supporting PCI Express (Rev 1.0/2.0), 10GigE, Gigabit Ethernet, Serial RapidIO (Rev 1.0/2.0), and SerialLite II standards. It contains up to 530k equivalent LEs, over 20 Mbits of embedded memory, and 1,024 embedded 18x18 multipliers. The FPGA implements BittWare’s Atlantis FrameWork and provides seamless routing of all on-board data, I/O, and memory.

Block Diagram

Fat Pipes, Common Options, and I/O Interfaces

The Altera Stratix IV GX FPGA interfaces to three ports (1, 2, & 3) in the AMC common options region, and 16 ports in the AMC fat pipes region (4 - 15, 17 - 20). These 19 ports provide a network data and control switch fabric interface on the AMC connector, with 12 supporting up to 6.25 GHz, three supporting up to 3.125 GHz, and the remaining four providing LVDS rear-panel I/O. All AMC clocks are also connected to the Stratix IV GX.

The front panel provides an additional four SerDes via an Infiniband-type connector, along with 10/100 Ethernet, two RS-232 ports, and a JTAG port for debug support.

BittWare's ATLANTiS™ FrameWork

BittWare’s ATLANTiS FrameWork (AFW) provides reconfigurable FPGA components, along with the infrastructure necessary to implement, simulate, synthesize, validate, and deploy a complete FPGA application on the Stratix IV GX. AFW delivers fully validated FPGA physical interfaces for all board-level I/O and communications, including high speed SerDes and external memory control, along with resource management components such as buffering, DMA engines, and arbitration. Each component can be easily monitored and controlled via an addressed path implemented using Altera’s open standard Avalon Memory Mapped Interface. Similarly, Altera’s open standard Avalon Streaming Interface is used to implement point to point data transport between ATLANTiS components. A set of reconfigurable fabric components such as multiplexers, switches, decoders, and FIFOs expand the interconnect options for both memory mapped and streaming interfaces. AFW removes the burden of reinventing low-level IP for the FPGA, thus freeing developers to focus on unique value-added development.

FINe™ Host/Control Bridge

BittWare’s FINe Host/Control Bridge implements a complete control plane interface for the S4AM, facilitating separate control and data planes, and greatly simplifying the development of data plane I/O and processing. Extensive software support is provided via BittWare’s BittWorks Toolkit including a Host Interface Library (HIL) which supports run-time command and control, and the DSP21K Toolkit for development and debugging.

Board Architecture

FPGA

• Altera® Stratix® IV GX FPGA (4SGX230/530)
• BittWare’s ATLANTiS™ FrameWork
• 16 full-duplex, high-performance, multi-gigabit SerDes transceivers @ 6.25 GHz
• Three full-duplex, multi-gigabit SerDes transceivers @ 3.125 GHz
• Over 530k equivalent LEs
• Over 20 Mbits of RAM
• Over 1,024 embedded multipliers

External Memory

• Two banks of up to 1 GByte DDR3 SDRAM configured as x32
• Two banks of up to 9 MBytes QDRII+ SRAM configured as x18
• 64 MBytes of Flash memory for booting FPGA and FINe

Fat Pipes Interface

• 12 ports (4 - 11, 20 - 17) @ up to 6.25 GHz via ATLANTiS™ FrameWork, configurable to support PCI Express (Rev 1.0/2.0), Serial RapidIO (Rev 1.0/2.0), GigE, 10GigE/XAUI
• Four ports (12 - 15) of LVDS I/O (4 In, 4 Out)

Common Options Interface

• BittWare’s FINe™ Host/Control Bridge providing Gigabit Ethernet on port 0
• Ports 1, 2 & 3 via ATLANTiS™ FrameWork, configurable to support PCI Express, Serial RapidIO, and GigE

Other AMC Edge Connections

• All AMC clocks brought to ATLANTiS
• Module Management Control (MMC) Interface implementing IPMI for temperature monitoring and hot-swap support
• Connectorless footprint for Agilent / Tektronix logic analyzers

AMC Front Panel I/O

• 10/100 Ethernet to FINe
• RS-232 port to Stratix IV GX
• RS-232 port to FINe
• JTAG debug interface to the Stratix IV GX

SFP / SFP+ FMC

• 4 SFP/SFP+ transceivers on front panel connected to FPGA via SerDes
• EEPROM available via I2C

Size

• AMC full-size, single width format compatible with AMC.0 specification R2.0

Software Support

Host Interface

• BittWare’s software development kit for Windows® and Linux contains C-callable libraries for board control and communications routines
• Porting kit available for other operating system platforms

Development Tools

• Altera’s Quartus® II software
• BittWare’s FPGA Developers Kit with modules for ATLANTiS framework (I/O, routing, and processing), memory interfacing, and DMAs

Ordering Information

SP/S4AM-RW-YY-Z-AABB-CDEFG-HHIJK

RW: Ruggedization

0U = Commercial (0C to 50 C)*

YY: SFP Transceiver

00 = No transceiver (default)

Z: Front Panel Input Clock

0 = Not Installed*

1 = Installed†

AA: FPGA Size

23 = Altera Stratix IV GX 230 FPGA*

53 = Altera Stratix IV GX 530 FPGA†

BB: FPGA Speed Grade

C2 = Commercial Speed Grade 2†

C3 = Commercial Speed Grade 3*

C4 = Commercial Speed Grade 4†

I3 = Industrial Speed Grade 3†

I4 = Industrial Speed Grade 4†

C: DDR3 Bank A Size

0 = None†

7 = 256 MB*

8 = 512 MB†

9 = 1 GB†

D: DDR3 Bank B Size

0 = None†

7 = 256 MB*

8 = 512 MB†

9 = 1 GB†

E: QDRII+ Bank A Size

0 = None*

2 = 9 MB†

F: QDRII+ Bank B Size

0 = None*

2 = 9 MB†

G: FINe Flash Size

5 = 64 MB†

6 = 128 MB*

HH: Front Panel

F3 = Full Size SPFM Cutout*

I: Front Panel SerDes

0 = Not Populated*

J: VITA-57 Vadjust

0 = Any Vadj but 3.3V†

1 = Vadj of 2.5V or 3.3V*

K: VITA-57 VioB

0 = Any VioB but 3.3V†

1 = VioB of 2.5V or 3.3V*

* Default

† Contact Sarsen Technology for availability

Please call us on +44 1672 511166 or send an email to info@sarsen.net to learn more about the features of BittWare's Altera Stratix IV GX FPGA COTS solutions.