Reef-PMC+ Reconfigurable Xilinx Virtex-II FPGA PMC+ Mezzanine Card

BittWare's Reef-PMC+ is a reconfigurable FPGA board combining the power of the Xilinx XC2V1000 Virtex-II FPGA and the Analog Devices ADSP-21160 SHARC DSP. Configurable for nearly any application, the Reef-PMC+ allows system designers to take advantage of both the flexibility of a reconfigurable FPGA and the processing power of a general purpose DSP.

Xilinx XC2V1000 Virtex-II FPGA The Xilinx XC2V1000 Virtex-II features up to 1 million system gates, a flexible digital I/O interface, and reconfigurable computing blocks. The XC2V1000 features: 11,520 logic cells 720 BRAM (Kbits) 40 18x18 Multipliers 8 Digital Clock Management Blocks 160 Max Dist. RAM Kb 432 Max Available User I/O

The ADSP-21160 DSP provides additional I/O and processing power for the board. Rounding out the Reef's feature set are a 64/66 PCI interface, a 64-512 MB bank of SDRAM and 2MB of Flash memory.

The host of features available on the Reef-PMC+ give designers the tools they need to implement complete DSP subsystems, including complex digital interfaces, general purpose compute engines, special purpose computing blocks and large data buffers. The Reef's ability to completely reconfigure on the fly further enhances its utility.

Xilinx Virtex-II Reconfigurable FPGA

The Virtex-II reconfigurable FPGA from Xilinx is a powerful solution for custom digital interfaces based on IP cores and customised modules. The Reef-PMC+ features a flexible digital I/O interface that provides up to 68 front panel primary user I/O pins each of which is individually configurable for any of nineteen single-ended I/O standards and six differential I/O standards including LVDS, SSTL, HSTL II and GTL+. Any two I/O pins can be used as a differential pair providing maximum board layout flexibility.

The Virtex-II FPGA also provides 38 secondary user I/O pins which are available on two optional connectors. The Virtex-II is configured on power-up by the host or an on-board EPROM and supports reconfiguration "on-the-fly" from either the host or the DSPs on the host card.

SharcFIN ASIC 64-Bit, 66MHz PCI Bus Interface

BittWare's SharcFIN® ASIC provides a full 64-Bit, 66MHz bus mastering PCI interface and an SDRAM controller to interface the SDRAM and the Xilinx Virtex-II to the PCI host. The SharcFIN interfaces to the PCI bus at 64-Bits, 66MHz for 528MB/s burst throughput and provides both bus mastering DMA capability and slave access to the SDRAM and Virtex-II.

I/O Interface Options

The Virtex-II can send and receive data via the SharcFIN, which provides the 64/66 PCI interface, or via a high-density 68-pin I/O connector on the front panel. The Virtex-II also supports two link ports and a serial port that connect it directly to the ADSP-21160, allowing the DSP to move data between the Virtex-II and the host via the PMC+ interface. A local parallel bus gives the Virtex-II high-speed access to the SDRAM, the SharcFIN and the ADSP-21160.

In addition to the 68-pin front panel I/O connector, two optional I/O connectors are also available. One provides 68 pins of I/O and the other provides 4 pins of I/O for a total of 140 user I/O pins. Both 68-pin connectors are available with optional LVDS input terminations, either 34 pairs or 17 pairs.

PMC+ Interface

The Reef-PMC+ is fully compatible with any PMC capable base board. When attached to one of Bittware's PMC+ base boards it also supports BittWare's PMC+ extensions which include four link ports directly to the Xilinx Virtex-II FPGA. The PMC+ link ports are configurable for BittWare's TigerSHARC DSP (ADSP-TS101 / ADSP-TS201) or Hammerhead (ADSP-2116x) base boards and are an ideal way to move high-speed data directly to the DSPs.

Software Development Tools

BittWare offers an FPGA developer's kit and a host interface library that allows designers to easily develop code and integrate the Remora-PMC+ into their systems. Xilinx also provides a complete suite of development tools for the Virtex-II FPGA. Xilinx provides all of the tools required to enable high-performance system design with Virtex-II FPGAs. In addition to having the fastest development software platform, Xilinx enhances the complete design process by providing world class IP core solutions, verification tools, and information resources. Please note that the end-user is responsible for generating, assembling and debugging all application-specific FPGA design for the Virtex-II; however, custom FPGA design is available from BittWare.

Ordering Options

The BittWare Reef-PMC+ is available with a number of standard configurations:

• I/O Connector A: 1= No terminations, 2= 34 pairs LVDS input terminations, 3= 17 pairs LVDS input terminations, X= Custom
• B: I/O Connectors B & C: 0= Not populated, 1= No terminations, 2= 34 pairs LVDS input terminations, 3= 17 pairs LVDS input terminations
• C: I/O Connector Grounding: 0= No ground, 1= Ground 4 corners on connectors A and B
• D: JTAG Connectors: 0= Not populated, 1= Populated. Please note that the installed JTAG connector violates the PMC height specification for a single slot

For more details of any BittWare Xilinx FPGA PMC+ product, please contact Sarsen Technology on +44 1672 511166 or visit the BittWare web site: BittWare Inc.