|
Quad ADSP-TS101 TigerSHARC PCI board
BittWare’s Tiger-PCI (TSPC) board features the processing power of four
250 MHz Analog Devices ADSP-TS101S TigerSHARC DSPs. The PCI board incorporates a 64-bit 66
MHz PCI interface and shared memory, including up to 256 MB SDRAM and 8 MB Flash. The board
also features a variety of I/O interfaces, which include a PMC site and external link ports.
ADSP-TS101S DSPs
The TSPC’s four ADSP-TS101S TigerSHARC DSPs share
a common 83.3 MHz local bus, which also provides access to the SDRAM
and SharcFIN ASIC. The TigerSHARC provides 12 Gbytes/sec of internal
memory bandwidth and features 6 Mbits of on-chip SRAM. It supports
both fixed and floating point operation, providing 1500 MFLOPS of
processing power for 32-bit floating point operations and 6 GOPS for
16-bit fixed point operations.
 |
Providing the backbone of the TSPC’s architecture is BittWare’s SharcFIN ASIC
for the ADSP-TS101S. The SharcFIN features a comprehensive set of bus interfaces and peripherals
for the ADSP-TS101S DSPs and provides a clean board-level implementation.
|
It integrates a full 64-bit 66 MHz master PCI interface, an extensive flag
and interrupt multiplexer, and a peripheral bus that interfaces the DSPs to peripherals such as
the Flash memory.
Features:
- Four 250 MHz ADSP-TS101S TigerSHARC® DSPs
- 6 Mbits of on-chip SRAM per DSP
- Static superscalar architecture
- Fixed or floating point operations
- 12 Gbytes/sec of internal memory bandwidth
- 6000 MFLOPS (floating point) or 24 GOPS (fixed point) of DSP processing power
- SharcFIN 64-bit, 66 MHz PCI bus interface
- 64 - 256 MB SDRAM
- 8 MB Flash memory
- PMC site with PMC+ extensions for BittWare’s PMC+ I/O modules
- Four external link ports Two link ports per DSP dedicated for interprocessor
communication
- Complete software support
SharcFIN™ ASIC
Providing the backbone of the TSPC’s architecture is BittWare’s SharcFIN ASIC for the ADSP-TS101S. The SharcFIN features a comprehensive set of bus interfaces and peripherals for the ADSP-TS101S DSPs and provides a clean board-level implementation. It integrates a full 64-bit 66 MHz master PCI interface, an extensive flag and interrupt multiplexer, and a peripheral bus that interfaces the DSPs to peripherals such as the Flash memory.
I/O Interfaces
I/O interfaces on the TSPC include four external link ports and a PMC site with BittWare’s PMC+ extensions. The PMC site has front panel access and is compatible with standard PMC modules or with BittWare’s PMC+ I/O modules. BittWare PMC+ modules have access to the site’s PMC+ extensions, which include four link ports.
Each DSP has four 250 Mbytes/sec link ports, which allow high-speed communication between TigerSHARC DSPs either on the same card or on other cards. One link per DSP connects to an external connector, one connects to the PMC+ interface, and two are available for interprocessor communication.
This architecture combines robust TigerSHARC processing with the versatile
Virtex-II Pro FPGA from Xilinx to offer ultra high performance and unprecedented I/O bandwidth.
The T2PC matches a cluster of four ADSP-TS201 TigerSHARCs with:
- High-bandwidth, low-latency off-board I/O, reconfigurable for nearly any application
- High-speed interprocessor communication network to facilitate scalability
- SharcFIN PCI-DSP bridge for integrating DSPs with PCI bus and other peripherals
- Comprehensive software for ease-of-use
High Performance TigerSHARC Processing
The T2PC features a cluster of four ADSP-TS201 TigerSHARC DSPs, which are
interconnected by a 64-Bit, 100 MHz cluster bus. The ADSP-TS201 processor operates at up to
600 MHz, providing 3.6 GFLOPS of peak processing power.
Because of its superscalar architecture, the ADSP-TS201 is also efficient
at fixed-point processing, with each DSP supporting 14.4 BOPS of processing. Along with 24
Mbits of on-chip RAM, each DSP also boasts four high-speed LVDS link ports running at up to
1 GB/sec each. Two link ports from each DSP create an interprocessor communications ring, and
the remaining two link ports are routed to the on-board FPGA.Please follow the links below for
details of BittWare development boards using both the first and second generation families of
TigerSHARC® processors.
SharcFIN PCI Bridge & Host Interface
The T2PC features a BittWare SharcFIN PCI-DSP bridge chip that gives
the DSPs low-overhead access to the host and PMC site via the 64-Bit, 66 MHz PCI interface.
The SharcFIN also provides a general purpose peripheral bus that allows the
DSPs to access the Flash and the FPGA control registers. It also provides host access to the
DSPs, on-board SDRAM, FLASH and FPGA control registers.
Low-Latency Off-Board I/O
The T2PC boasts a tremendous amount of I/O bandwidth and options, including
eight LVDS link ports, a PMC site with BittWare’s PMC+ I/O extensions, high-performance
digital I/O headers,and eight RocketIO high-speed serial transceivers. Total potential I/O
bandwidth is greater than 6 GB/sec.
Xilinx Virtex-II Pro FPGA
A Xilinx Virtex-II Pro (XC2VP20) FPGA adds tremendous flexibility to the
board and is useful for routing communications, translating protocols, and implementing
algorithms. It is used to implement eight on-board TigerSHARC link ports and supports a
variety of external digital I/O (DIO), flags, and interrupts. The Virtex-II Pro’s eight
RocketIO high-speed serial transceivers, which are brought off-board, provide additional
external communications.
ATLANTiS: A Superior Architecture for a Superior Processor
To facilitate off-board I/O and provide communications routing and
processing, the T2PC features BittWare’s ATLANTiS architecture, which is implemented in the
Xilinx Virtex-II Pro FPGA. All off-board I/O for the board, which includes external link ports
and digital I/O blocks, is routed through the FPGA, which can support a throughput of 4 GB/sec.
By tightly integrating the DSPs, PCI bridge, PMC interface, and I/O peripherals with the
on-board FPGA, ATLANTiS gives designers nearly infinite options for configuring and routing
the I/O.
TigerSHARC Link Ports
The eight bi-directional TigerSHARC link ports routed to the ATLANTiS FPGA
provide 4 GB/sec of data transfer between the DSP cluster and the FPGA. Using its eight RocketIO
high-speed serial transceiver channels and its digital I/O blocks, the FPGA can communicate
off-board at greater than 4.8 GB/sec. It can be configured to connect the I/Os to each other or
to the ADSP-TS201 link ports, allowing any combination of inputs and outputs to be routed together. The digital I/O blocks include PMC+ and high-performance off-board connectors. Each digital I/O signal can also be individually configured as single-ended or LVDS. ATLANTiS adds tremendous flexibility to the DSP subsystem, allowing system designers to route the link ports and digital I/O blocks as their specific applications require.
Development Tools
BittWare offers complete software development tools
that allow designers to easily develop application code and integrate
the BittWare TigerSHARC-PCI-X card into their systems.
BittWare's BittWorks DSP21k Toolkit allows users to easily develop
application code and simply comunicate with all of BittWare's ADSP-TS201 DSP cards. The board
is fully compatible with Analog Devices' VisualDSP++® and supports
in-circuit emulation. It is also supported by TS-Lib, BittWare's
highly-optimized, C-callable runtime libraries, and by SDL's DSPdeveloper,
target for MathWorks MATLAB, Simulink® and Real-Time Workshop®.
Full technical advice on the BittWare hardware and software embedded COTS
TigerSHARC DSP solutions is available from Sarsen Technology on +44 1672 511166.
|
