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XPedite2770


Overview

AMD Versal® Prime VM1402 ACAP-Based 3U VPX FPGA Module

The XPedite2770 from Extreme Engineering Solutions, is a high-performance, reconfigurable, conduction-cooled, 3U VPX processing module based on the AMD (formerly Xilinx) Versal® Prime Adaptive Compute Acceleration Platform (ACAP).
With multiple high-speed fabric interfaces and 16 GB of LPDDR4 ECC SDRAM in two channels, the XPedite2770 is ideal for customizable, high-bandwidth, signal-processing applications. It integrates SecureCOTS™ technology with a Versal® Prime VM1402 ACAP for hosting custom functions to protect data from being modified or observed and provides an ideal solution when stringent security capabilities are required.
 

Technical

  • AMD (formerly Xilinx) Versal® Prime VM1402 ACAP
  • 3U VPX (VITA 46) module
  • Compatible with multiple VITA 65 OpenVPX™ slot profiles and SOSA-aligned options
  • 16 GB of LPDDR4 ECC SDRAM in two channels
  • 4 Gbit of QSPI FPGA configuration flash
  • 32 GB of SLC NAND flash
  • XMC site with one x8 PCI Express interface and rear I/O support
  • Two 10/100/1000BASE-T Ethernet ports
  • Two GTY High-Speed Serial (HSS) lanes capable of 10GBASE-R Ethernet (contact X-ES for IP requirements)
  • Two x4 PCI Express Gen3 interfaces to P1.A and P1.B
  • One x1 PCI Express Gen3 interface
  • One RS-232/422/485 serial port
  • One UART/RS-232 maintenance port
  • 14 LVDS GPIO
  • 16 single-ended (SE) GPIO
  • Linux Yocto support
  • FPGA Development Kit (FDK)

Specifications

FPGA
  • AMD (formerly Xilinx) Versal® Prime VM1402 ACAP for high-performance logic and DSP applications
  • Dual-core ARM® Cortex®-A72, 48 KB/32 KB L1 cache with parity and ECC; 1 MB L2 cache with ECC
  • Dual-core ARM® Cortex®-R5F, 32 KB/32 KB L1 cache, and 256 KB TCM with ECC

Memory
  • 16 GB of LPDDR4 ECC SDRAM in two channels
  • 32 GB of SLC EMMC NAND flash
  • 4 Gbit of QSPI FPGA configuration flash

VPX (VITA 46) P0 I/O
  • Two IPMB connections to an IPMI controller

VPX (VITA 46) P1 I/O
  • Two x4 PCI Express Gen3-capable interfaces to P1.A and P1.B
  • Two GTY High-Speed Serial (HSS) lanes capable of 10GBASE-R Ethernet (contact X-ES for IP requirements)
  • XMC P16 I/O, mapping P1w9-X12d per VITA 46.9

VPX (VITA 46) P2 I/O
  • Two 10/100/1000BASE-T Ethernet ports
  • Six LVDS GPIO
  • One x1 PCI Express Gen3-capable interface (contact X-ES for SATA support options)
  • One RS-232/422/485 serial port
  • Build option for eight LVDS and 16 SE GPIO from the FPGA, or XMC P16 I/O mapping P2w9-X16s+X8d

XMC Site
  • One x8 PCI Express Gen3-capable interface

Development Support
  • U-Boot firmware
  • Linux Yocto support

Physical Characteristics
  • 3U VPX-REDI conduction- or air-cooled form factor
  • Dimensions: 100 mm x 160 mm
  • 0.8 in. pitch without solder-side cover
  • 0.85 in. and 1.0 in. pitch with solder-side cover and Two-Level Maintenance (2LM) support

Environmental Requirements
Contact factory for appropriate board configuration based on environmental requirements.
  • Supported ruggedization levels 
  • Conformal coating available as an ordering option

Power Requirements
  • Power will vary based on configuration and usage. Please consult factory.

Ordering information

There are a range of options available. Please contact Sarsen to discuss your project requirements.