Technical
Supports four 12-bit ADC channels with sample rates up to 6GSps and two 16-bit DAC channels with sample rates up to 12GSps. Built around the Analog Devices Mixed-Signal Front End (MxFE) ADC/DAC devices, the QM61 offers optional (bypassable) built-in digital up and down converters and other optional DSP features targeted at either wideband or multiband, direct-to-RF applications. The QM61 is targeted at software defined radio (SDR), radar, electronic warfare and other applications requiring superior ADC and DAC performance.
Specifications
General
- Uses two Analog Devices Mixed-Signal Front End (MxFE) AD9082 ADC/DACs
- Optional Integrated DSP to offload FPGA processing
- Supports JESD204B/C interface with 32 lanes up to 24.75 Gbps
- Capability to have four ADC and two DAC channels in one 3U OpenVPX slot when plugged into WILDSTAR OpenVPX FPGA mainboards
- Capability to have eight ADC and four DAC channels in one 6U OpenVPX slot when plugged into WILDSTAR OpenVPX FPGA mainboards
- Compatible with any WILDSTAR mainboard with a WFMC+ slot
- Firmware and Software for four channel data transmit interface and clock trigger synchronization provided in CoreFire Next and VHDL source
- Designed with configurable input and output circuitry for interfacing with a wide range of tuners
- Out-of-the-box optimization with Analog Devices’ high density, 2-18GHz, 3U VPX Tuner (Contact factory for more information)
ADC Performance
- 6GSps 12b ADC Speed Grade (Analog Devices AD9082)
- Up to 4 channels
- Resolution: 12 Bits
- Analog Bandwidth: >6GHz
- Run Time Selectable ADC Decimation: 1-40x
- ADC Inputs have a run-time selectable Active or Passive Path
- Active Path
- Amplification
- Band Pass Filtering (default is tailored to 2nd Nyquist, 2GHz IBW)
- Digital Step Attenuation (0-15dB)
- Slope compensation
- Passive Path with Low Pass Filtering
DAC Performance
- 12GSps 16b DAC Speed Grade (Analog Devices AD9082)
- 2 channels
- Resolution: 16 Bits
- Analog Bandwidth: >6GHz
- Run Time Selectable DAC Interpolation: 1-40x
Digital Features
- Configurable or bypassable DDCs and DUCs
- 8 fine complex DUCs and 4 coarse complex DUCs
- 8 fine complex DDCs and 4 coarse complex DDCs
- 48-bit NCO per DUC or DDC
- Programmable 192-tap PFIR filter for receive equalization
- Supports 4 different profile settings loaded via GPIO
- Receive AGC support
- Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Transmit DPD support
- Fine DUC channel gain control and delay adjust
- Coarse DDC delay adjust for DPD observation path
- Aux Features
- Fast frequency hopping and direct digital synthesis (DDS)
- Low latency loopback mode (receive datapath data can be routed to the transmit datapaths)
Clock Performance
- Software-selectable external clock input or onboard PLL clock
- Run Time Clock Source Selection
- External Full Rate Clock
- Internal PLL with Run Time Selectable Reference Source
- External RF Connector
- Internal Oscillator
- Mainboard/Backplane provided Reference
I/O Connectors
- Eight 50Ω Front Panel or VITA 67 Connectors
- Four Analog ADC Inputs
- Two Analog DAC Outputs
- One External Sample Clock Input
- One High Precision Trigger Input
- 2.5V LVPECL
- 3.3V LVPECL
- 2.5V LVCMOS
- 3.3V LVCMOS
Clock Synchronization
- All ADCs and DACs across multiple mezzanine cards can be synchronized using WILDSTAR Clock Distribution Boards and select WILDSTAR Backplanes
Mechanical and Environmental
- Integrated Heatsink and EMI / Crosstalk Shields
- Commercial and Industrial Temperatures Available
- Air Cooled, Conduction Cooled and Air-Flow-Through Cooled supported
Ordering information
There are a range of options available. Please contact Sarsen to discuss your project requirements.