Ultra Low latency from ADC SMA input to DAC SMA output
Digital Bypass Mode has built-in run-time adjustable delay providing additional delay from 0ns up to 124 Sclk periods
Capability to have two ADC channels and two DAC channels in one 6U OpenVPX slot when plugged into WILDSTAR OpenVPX FPGA cards
Compatible with any WILDSTAR mainboard with a WFMC+ slot
Firmware and Software Board Support Interface provided in CoreFire Next and VHDL source
Sample Rate: 400 – 2500MSps
ADC Resolution: 10 bits
DAC Resolution: 12 bits
One Analog Input
One Analog Output
One External PLL Reference Input
One High Precision Trigger Input
One Differential External Clock Input
Integrated Heatsink and EMI / Crosstalk Shields
Commercial and Industrial Temperatures Available
Air Cooled and Conduction Cooled supported
Software-selectable external clock input or onboard PLL clock
All ADCs and DACs across multiple mezzanine cards can be synchronized to the same sample using WILDSTAR Clock Distribution Boards
Provides capability to configure 20+ ADC and DAC channels in one COTS Annapolis 19” OpenVPX Chassis
Sarsen Technology Limited is registered in England & Wales. Registration number: 03902012.
Registered office: 23-24 High Street, Marlborough, Wiltshire, SN8 1LW