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WB3XR0


Overview

SOSA-Aligned 3U Dual RFSoC FPGA Board with Analog Interface Mezzanine Site

The WILDSTAR 3XR0 FPGA Processor card from Annapolis Micro Systems is 100GbE-enabled, SOSA-aligned, and it leverages the processing and A/D & D/A converting power of two Gen 3 Xilinx UltraScale+™ RFSoC FPGAs. The 3XR0 is the first board from Annapolis to offer a full-length coax-connected Analog Interface Mezzanine Site

This mezz site can be populated with a direct RF digitization card, or a 3rd party analog super-heterodyne tuner to allow digitisation of 18+GHz signals. An integrated tuner delivers much lower SWaP-C than a separate standalone tuner, while maintaining the ability to upgrade the tuner and digitiser/processor separately.

In addition to two Gen 3 Zynq UltraScale+ RFSoC FPGAs, an on-board Xilinx MPSoC provides high performing yet low power self-hosting capability thanks to the power-efficient ARM cores.

For maximum flexibility, the 3XR0 can be built to support SOSA and/or VITA 65 backplane slot profiles architectures.

The 3XR0 is hot swappable, allowing for more system reliability. This feature is unique to Annapolis

Specifications

General Features

  • Supports 3rd party/customer-designed Analog Interface Cards for direct RF digitization or 18+GHz superhet tuning
  • Two Gen 3 Zynq® UltraScale+™ RFSoC FPGAs (XCZU43DR). Other configurations also available – contact factory for part number options.
    • Quad-core 64-bit ARM® Cortex-A53
    • Dual-core 32-bit ARM® Cortex-R5F
    • Up to 2.8 Mb of UltraRAM Per RFSoC
    • 8GB per RFSoC
  • One Zynq® UltraScale+™ MPSoC EV Motherboard Controller (XCZU5EV)
    • Quad-core 64-bit ARM® Cortex-A53
    • Dual-core 32-bit ARM® Cortex-R5F
    • Up to 2.2 Mb of UltraRAM
    • 4GB of DDR4 DRAM
    • Board support enabling user customization of ZYNQ+ design
    • Multiple levels of hardware and software security
  • VITA 46.11/SOSA IPMC Support

ADC & DAC I/O

  • ADC
    • Channels: 4 or 8
    • Max Sample Rate: 5.0GSps
    • Resolution: 14 bit
  • DAC
    • Channels: 4 or 0
    • Max Sample Rate: 10.0GSps
    • Resolution: 14 bit
  • Backplane RF support with VITA 67
  • HSS connections can support protocols such as 10/40/100Gb Ethernet and Aurora or user designed protocols. Some HSS interfaces also support PCIe using FPGA hard blocks

Mechanical and Environmental

  • 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 or 1.5” VITA 48.8 (AFT) spacing
  • Supports OpenVPX payload profiles such as:
    • SLT3-PAY-2F1F2U1J-14.6.5-n
    • SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
    • SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (SOSA Secondary)
  • Available with 85° C ambient air temperature or card edge support and -55° C power-on
  • Available with -65° C to 105° C storage temperature
  • Air, Air-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard

Application Development

  • Open Project Builder Application Design Suite
    • Full Board Support Package for Fast and Easy Application Development
    • Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
    • Develop in GUI environment or create VHDL and use HDL environment
    • Built-in Debugger for Hardware in the loop Debugging
    • Supports High-Level Synthesis (HLS) Design Flow
  • VHDL BSP packages including full synthesis and simulation support
  • Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
  • IOPE JTAG Access through RTM or Ethernet
  • Board control and status monitoring can be local and/or remote (via Ethernet)

Ordering information

There are a number of configurations available. Please contact Sarsen Technology to dicuss the options best suited to your application.

Associated products