WB6XV4 - SOSA Aligned 6U VPX Xilinx Versal 100GbE FPGA Board - Sarsen Technology
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6XV4


Overview

SOSA Aligned 6U VPX Xilinx Versal 100GbE FPGA Board

The WILDSTAR 6XV4 from Annapolis Micro Systems integrates one of Xilinx's new Versal™ Premium VP2802 FPGAs. It is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled. It has the option for the most optical connections of our 6U Versal baseboards.

These FPGA boards are SOSA-aligned Plug-In Cards (PIC). They include one Versal Premium VP2802 FPGA and have eight 32-bit LPDDR4 DRAM ports running up to 3700 MT/s.

The on-board dual-core ARM CPU runs up to 1.4 GHz and can be used for local application requirements. It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs, and can also be used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1 or 10GbE.

WILDSTAR 6XV4 6U OpenVPX FPGA processor boards are hot swappable in air cooled environments allowing for better system reliability, and are available in Air-Flow-Through, Liquid-Flow-Through or Conduction Cooled variants.

 

Technical

General Features

  • One Versal™ Premium VP2802 FPGA
    • Up to 14,352 DSP Slices and 7,352,000 logic cells
    • Up to 717 Mb of High Bandwidth, Low Latency UltraRAM
    • Eight 32-bit LPDDR4 DRAM ports running up to 3732 MT/s
    • Dual-core 64-bit ARM® Cortex-A72 running up to 1.4GHz
    • Dual-core 32-bit Cortex-R5F real-time processor running up to 600MHz
  • Multiple levels of hardware and software security
  • Supports up to 472 AI Engine Tiles and 118Mb of AI Engine Data Memory
  • Up to twenty-four 100G Optical Transceivers to VITA 66 Backplane Interface

Specifications

Mechanical and Environmental

  • 6U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
  • Supports OpenVPX payload profile:
    • SLT6-PAY-4F2Q1H4U1T1S1S1TU2U2T1H-10.6.4-n
  • Available with -40°C to 81°C cold wall operational temperature and -55°C cold start
  • Available with -62°C to 105°C storage temperature
  • Air-Flow-Through, Liquid-Flow-Through or Conduction Cooled
  • Only requires +12V and +3.3VAUX from backplane
  • Developed in alignment with the SOSA™ Technical Standard
  • RT3 backplane connectors for 100G support

Application Development

  • Full Board Support Package for fast and easy Application Development
  • Includes source for all provided software components and examples on Versal PEs
  • Open CoreFire™ support
    • HDL generation
  • Three development flow paths:
    • Traditional RTL development flow
      • HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream
    • *NEW* Dynamic Function eXchange (DFX) RTL development flow
      • Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
      • Design refactors and testing iterations significantly sped up
      • CIPs function remains active while fabric is reloaded
    • *NEW* Vitis™ Platform Project development flow

Ordering information

There are a number of configurations available. Please request a quote via the orange button and we will get in touch to discuss your requirements.

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