Products

WS3XBP-67

Overview

WILDSTAR 2-Channel Direct RF 3U OpenVPX Module

The WILDSTAR™ 2-Channel Direct RF 3U OpenVPX Module from Annapolis Micro Systems is a factory assembled solution that is 100GbE-enabled, SOSA-aligned, and highly rugged and thermally-controlled.

Customers can directly digitise and process wideband signals with this high-performance 64 GSps Direct RF Module. The solution is configured with the WB3XBP Processor Baseboard and WWDME1 ADC/DAC Mezzanine in one 3U VPX slot. High-performance digitising and processing are powered by two UltraScale+™ FPGAs and a mezz-mounted 64 GSps Direct RF Transceiver.

VITA 66/67 optical/RF backplane support is included.

Technical

General Features

One Virtex® UltraScale+ XCVU5P/XCVU7P FPGA
- Up to 5520 DSP Slices and 1,724,000 logic cells
- Up to 270 Mb of High Bandwidth, Low Latency UltraRAM
- GTH/GTY transceivers operating up to 32.75 Gb/s
- Two 80-bit DDR4 DRAM ports running up to 2400 MT/s
One Zynq® UltraScale+ MPSoC EV Motherboard Controller(XCZU7EV)
- Quad-core 64-bit ARM® Cortex-A53 running up to 1.2GHz
- Dual-core 32-bit Cortex-R5 real-time processor running up to 533MHz
- 1728 DSP Slices, 504,000 logic cells and 27Mb of UltraRAM
- Board support enabling user customization of Zynq+ design
One Jariet Technologies Electra-MA Transceiver
Firmware and Software for four channel data transmit interface and clock trigger synchronisation provided in CoreFire Next and VHDL source
Multiple levels of hardware and software security
VITA 46.11/SOSA IPMC Support

Specifications

ADC Performance

40 to 64GSps ADC
2 Channels
10 Bit Resolution in full-Nyquist
- Spurs corrected to 12b resolution in full-Nyquist
Usable Analog Bandwidth: 36GHz
- 24 GHz -3dB Bandwidth
Maximum Instantaneous Bandwidth: 6.4GHz
Run Time Selectable ADC Decimation: 8-1024x
- 16b resolution for each I and Q decimated output
- 12b mode is also available

DAC Performance

40 to 64GSps DAC
2 Channels
10 Bit Resolution in full-Nyquist
Usable Analog Bandwidth: 36GHz
- 15 GHz -3dB Bandwidth at 64GSps
Maximum Instantaneous Bandwidth: 6.4GHz
Run Time Selectable DAC Interpolation: 8-1024x
- 16b resolution for each I and Q interpolated input
- 12b mode is also available

Front Panel and/or Backplane I/O

Nine 50Ω RF Mezzanine I/O
- Two Analog ADC Inputs
- Two Analog DAC Outputs
- One External Sample Clock Divide by 16 Input
- One Optional External PLL Reference Input
- One Optional High Precision Trigger Input. Options:
- 2.5V LVPECL
- 3.3V LVPECL
- 2.5V LVCMOS
- 3.3V LVCMOS
WILD FMC+ (WFMC+) next generation I/O site based on FMC+ specification
- Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
- Allows larger form factor Annapolis cards for higher I/O density
- Supports additional LVDS I/O for higher density ADC and DAC solutions
- Up to 32 High Speed Serial and 100 LVDS connections to FPGA
Backplane optical and RF support with VITA 66/67
HSS connections can support protocols such as 10/40/100 Gb Ethernet and Aurora or user designed protocols – some HSS interfaces also support PCIe using FPGA hard blocks

Mechanical and Environmental

3U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
Supports OpenVPX payload profiles such as:
- SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
- SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (SOSA Secondary)
Available with 85°C ambient air temperature or card edge support and -55°C power-on
Available with -65°C to 105°C storage temperature
Air, Air-Flow-Through or Conduction Cooled
Only requires +12V and +3.3VAUX from backplane
Developed in alignment with the SOSA™ Technical Standard
RT3 backplane connectors for 100G support

Clock Synchronisation

Software-selectable ADC/DAC clock source:
- External Divide by 16 Reference Clock
- External Divide by 16 Reference Clock + 2x Divide by 2 Clocks
- Internal PLL with Run Time Selectable Reference Source
  - External RF Connector
  - Internal Oscillator
  - Mainboard/Backplane provided Reference

Application Development

CoreFire Next Application Design Suite
- Full Board Support Package for Fast and Easy Application Development
- Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
- Develop in GUI environment or create VHDL and use HDL environment
- Built-in Debugger for Hardware in the loop Debugging
- Supports High-Level Synthesis (HLS) Design Flow
VHDL BSP packages including full synthesis and simulation support
Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
IOPE JTAG Access through RTM or Ethernet
Board control and status monitoring can be local and/or remote (via Ethernet)

Ordering information

There are a range of configuration options available.

Please contact Sarsen to discuss your project requirements or request a quote via the orange button.

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