Products

WS3XVD

Overview

SOSA Aligned 3U VPX Xilinx Versal 100GbE FPGA Board

These FPGA modules from Annapolis Micro Systems are SOSA-aligned Plug-In Cards (PIC). They package the WS3XVD Processor Baseboard and WLDM30 ADC/DAC Mezzanine in one 3U VPX slot. The high-performance assembly delivers ultra low and deterministic latency from ADC SMA input to DAC SMA output.

A full Board Support Package includes Open CoreFire Next™ support for HDL generation, and three development flow paths: traditional RTL, DFX RTL, and Vitis™.

Technical

General Features

One Versal™ Premium VP1702 FPGA
Up to 10,896 DSP Slices and 5,557,720 logic cells
Up to 541 Mb of High Bandwidth, Low Latency UltraRAM
Two 32-bit LPDDR4 DRAM ports running up to 3700 MT/s
Dual-core 64-bit ARM® Cortex-A72 running up to 1.4GHz
Dual-core 32-bit Cortex-R5F real-time processor running up to 600MHz
Ultra Low and Deterministic Latency from ADC SMA input to DAC SMA output
Digital Bypass Mode has built-in run-time adjustable delay providing additional delay from 0ns up to 124 Sclk periods
Optional Front panel RS422/RS485 GPIO interface
Optional 2/3×40/100G Optical Transceivers to VITA 66 Backplane Interface
Multiple levels of hardware and software security

Specifications

ADC And DAC Performance

Channels: 1 or 2
Max Sample Rate: 6.4GSps (Single Channel) and 3.2GSps (Dual Channel)
Resolution: 12 bits

Backplane I/O

Six 50Ω VITA 67 Connectors
Two Analog ADC Inputs
Two Analog DAC Outputs
One External PLL Reference Input
One Differential External Clock Input
Next Generation “WILD Mezzanine Card LVDS” (WMC-L) Site
Optimized for LVDS based ADC and DACs
For Latency Sensitive Applications
Annapolis Mezzanine products with “WL” prefix
SOSA-Aligned backplane I/O
Optimized for VITA 66/67 interfaces
Optimized for cooling
Allows larger form factor cards for higher IO density
Based on FMC+

Mechanical and Environmental

3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
Supports OpenVPX payload profile:
SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (no P2A connectivity)
Available with 85°C ambient air temperature or card edge support and -55°C power-on
Available with -65°C to 105°C storage temperature
Air, Air-Flow-Through or Conduction Cooled
Only requires +12V and +3.3VAUX from backplane
Developed in alignment with the SOSA™ Technical Standard 1.0
RT3 backplane connectors for 100G support

Clock Synchronization

Software-selectable external clock input or onboard PLL clock
All ADCs and DACs across multiple mezzanine cards can be synchronized to the same sample using WILDSTAR Clock Distribution Boards

Application Development

Full Board Support Package for fast and easy Application Development
Includes source for all provided software components and examples on Versal PEs
Open CoreFire Next™ support
HDL generation
Three development flow paths:

Traditional RTL development flow

HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream

*NEW* Dynamic Function eXchange (DFX) RTL development flow

Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
Design refactors and testing iterations significantly sped up
CIPs function remains active while fabric is reloaded

*NEW* Vitis™ Platform Project development flow

Ordering information

There are a number of configurations available. Please request a quote via the orange button and we will get in touch to discuss your requirements.

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