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A10PED


Overview

Dual Intel Arria® 10 GT/GX/SX FPGA PCIe Board with Dual 12x Avago Fiber Optic, QSFP, and HMC

The A10PED from BittWare is a full-length PCIe x8 card featuring two Intel Arria 10 GT/GX/SX FPGAs. The board offers flexible memory configurations, supporting a Hybrid Memory Cube along with over 64 GBytes of memory. Two 12x Avago fiber optic modules and a QSFP cage provide high-speed, low-latency I/O direct to the FPGAs. The A10PED also incorporates a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management.

Typical Applications
Network processing
Network Security
Compute and Storage
Instrumentation
Broadcast
SigInt
 

Technical

  • Two Intel Arria 10 GT/GX/SX FPGAs
  • Two PCIe x8 interfaces supporting Gen1, Gen2, or Gen3
  • Two 12x Avago fiber optic modules
  • QSFP cage for 4x 10GigE
  • Board Management Controller for Intelligent Platform Management
  • Utility I/O: USB 2.0, SATA, powered GPIO header, Ethernet
Memory options:
  • up to 4 GB Hybrid Memory Cube
  • up to 64 GBytes of DDR4 SDRAM with ECC
  • up to 144 MBytes QDR-IV
  • up to 288 MBytes QDR-II+

Specifications

A10PED Specifications

Board Specifications
FPGA
  • Intel Arria® 10 GT/GX/SX FPGA
  • Dual-core ARM Cortex-A9 MPCore; up to 1.5 GHz CPU operation per core (SX only)
  • High-performance, multi-gigabit SerDes transceivers @ up to 28 (GT) or 17 (GX/SX) Gbps
  • Up to 1150 (GX/GT) or 660K (SX) logic elements available
  • Up to 53 (GT/GX) or 42 (SX) Mb of embedded memory
  • 1.6 Gbps LVDS performance
  • Up to 3,376 (SX/GX) or 3,036 (GT) 18×19 variable-precision multipliers

On-Board Memory
  • Flash memory for booting FPGA

Hybrid Memory Cube (HMC)
  • Up to 4 GByte Hybrid Memory Cube connected to each FPGA via 16x SerDes

MicroSD Card
  • MicroSD card containing ARM/SoC OS and filesystem (SX only)

Optional SODIMM Memory
  • 2 per FPGA; can be any of the following:
  • DDR4: x72 w/ECC
    • Up to 16 GBytes per SODIMM
  • QDR-IV: 1x bank of x36
    • Up to 36 MBytes per SODIMM
  • QDR-II+: 1x bank of x36
    • Up to 72 MBytes per SODIMM

PCIe Interface
  • Two x8 Gen1, Gen2, Gen3 interfaces direct to FPGAs: one x8 interface (to FPGA A) in a standard slot; two x8 interfaces (one to each FPGA) requires bifurcated slot

USB Header
  • Micro USB port (USB 2.0) for debug and programming FPGA and Flash
  • Built-in Altera USB-Blaster

Avago Fiber Optic
  • Two 12x Avago fiber optic modules, connected to the FPGAs via 12 SerDes channels each

QSFP Cages
  • QSFP28 (zQSFP) cage on front panel connected directly to each FPGA via 2 SerDes (no external PHY)
  • Supports 4x 10GigE
  • Backward compatible with QSFP and can be optionally adapted for use as SFP+

Serial ATA
  • Two SATA connectors, connected to FPGAs

Ethernet
  • RJ-45 Ethernet jack for 1000BASE-T connection to the SoC (SX only, requires BWBO breakout board)

Board Management Controller
  • Voltage, current, temperature monitoring
  • Power sequencing and reset
  • Field upgrades
  • FPGA configuration and control
  • Clock configuration
  • I2C bus access
  • USB 2.0 and JTAG access
  • Voltage overrides

Size
  • Full-length, standard-height, double-wide PCIe slot card
 

Development Tools

System Development
  • BittWorks II Toolkit – host, command, and debug tools for BittWare hardware; Matlab API; source code porting kit also available

FPGA HDL Development
  • FPGA DevKit
    • Physical interface components
    • Board, I/O, and timing constraints
    • Example Quartus projects
    • Software components and drivers
  • Altera Tools
    • Quartus II software, including Qsys

Accessory Boards
  • BittWare TKBO timing kit for 1PPS and 10MHz clock input
  • BittWare BWBO breakout board for JTAG and RS-232 access

Ordering information

There are a wide rage of configurations available. Please contact Sarsen Technology to discuss your requirements.

Software

NEWS

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