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A10PL4


Overview

Intel Arria® 10 GT/GX FPGA Low Profile PCIe Board with Dual QSFP and DDR4

The A10PL4 from BittWare is an Intel Arria 10 FPGA PCIe board offering plenty of high speed serial I/O interfaces and debug support. Two QSFP cages are available, both connected to the Arria 10 FPGA removing latency in the external PHYs. The A10PL4 supports up to 32GB of DDR4 as well as flash memory with factory default and support for multiple FPGA images.

Technical

The A10PL4 is a low-profile PCIe board from BittWare, based on the Arria 10 GT/GX FPGA. The board offers flexible memory options, supporting up to 32GB of DDR4 memory and two front panel QSFP cages, each providing up to 100 Gbps. The QSFP SerDes channels are connected directly to the Arria 10 FPGA, and can optionally be adapted for SFP+.

The A10PL4 provides a variety of high-speed serial I/O interfaces, as well as a Board Management Controller (BMC) for advanced system monitoring, which greatly simplifies platform management.

Typical Applications
Network processing
Network security
Compute and storage
Instrumentation
Broadcasting

Specifications

FPGA
Intel Arria® 10 GT/GX FPGA
High-performance, multi-gigabit SerDes transceivers @ up to 28 (GT) or 17 (GX) Gbps
Up to 1150K logic elements available
Up to 53 Mb of embedded memory
1.6 Gbps LVDS performance
Up to 3,300 (GX) or 3,000 (GT) 18×19 variable-precision multipliers

On-Board Memory
Two banks DDR4 with ECC, up to 16 GBytes (x72) each
64 MBytes of Flash memory for booting FPGA

PCIe Interface
x8 Gen1, Gen2, Gen3 direct to FPGA

USB Header (Optional)
USB 2.0 interface for debug and programming FPGA and Flash
Built-in Altera USB-Blaster

Timestamp Headers (Optional)
1 PPS input
Reference clock input

QSFP Cages
2 QSFP28 (zQSFP) cages on front panel connected directly to FPGA via 8 SerDes (no external PHY)
Each supports 100GigE (GT only), 40GigE, or 4 10GigE
Backward compatible with QSFP and can be optionally adapted for use as SFP+

Board Management Controller
Voltage, current, temperature monitoring
Power sequencing and reset
Field upgrades
FPGA configuration and control
Clock configuration
I2C bus access
USB 2.0 and JTAG access
Voltage overrides

Size
Low profile (Half-height, half-length) PCIe slot card; x8 mechanical

Technical documents

Ordering information

There are a number of configurations available. Please contact Sarsen Technology to discuss the options.

NEWS