Products
3XVC
Overview
3U VPX SOSA Aligned 100GbE Versal FPGA Module with Maximum Optical Connections
The WILDSTAR 3XVC (WS3XVC) is a rugged, 3U OpenVPX FPGA processor board designed for high-performance, bandwidth-intensive applications. Aligned with the SOSA™ technical standard, the board is powered by AMD’s Versal™ Premium VP1702 FPGA, which delivers up to 10,896 DSP slices and over 5.5 million logic cells.
It is equipped with five 32-bit LPDDR4 DRAM ports running up to 3732 MT/s, alongside an onboard dual-core ARM Cortex-A72 CPU for handling local application requirements. Built for demanding defense and industrial environments, the board utilises ultra-high-speed RT4 backplane connectors for up to 200G support and comes in air-cooled, air-flow-through, and conduction-cooled configurations to ensure thermal stability.
Beyond its core processing power, the WS3XVC offers exceptional modularity and system reliability. It features a next-generation "WILD Mezzanine Card HSS" (WMC-H) site optimised for high-density JESD-based ADCs, DACs, and optical transceivers, accommodating VITA 66/67 optical and RF backplane interfaces.
Notably, the air-cooled version of the 3XVC is hot-swappable. This is a unique feature that allows operators to remove or replace a single board without shutting down the entire chassis, drastically improving system uptime.
Supported by a comprehensive Board Support Package and Open CoreFire™ development tools, the WS3XVC provides a secure, highly scalable solution for advanced digital signal processing and computing workloads.
Technical
Processor Engine: It integrates AMD’s Versal™ Premium VP1702 FPGA to handle extremely high-bandwidth workloads.
Connectivity & Bandwidth: The board is 100GbE-enabled and incorporates ultra-high-speed RT4 backplane connectors to support scaling up to 200G data transfers.
Standards Alignment: It is fully compliant with the SOSA™ (Sensor Open Systems Architecture) technical standard and OpenVPX (VITA 65) protocols.
Optical Capabilities: Compared to sister variants like the WS3XV1, the 3XVC model is explicitly optimised with maximum optical connections available.
System Reliability: The air-cooled version supports hot-swapping, allowing the board to be replaced or serviced without needing to shut down the entire system chassis.
Specifications
General Features
- One Versal™ Premium VP1702 FPGA
- Up to 10,896 DSP Slices and 5,557,720 logic cells
- Up to 541 Mb of High Bandwidth, Low Latency UltraRAM
- Five 32-bit LPDDR4 DRAM ports running up to 3732 MT/s
- Dual-core 64-bit ARM Cortex-A72 running up to 1.4GHz
- Dual-core 32-bit Cortex-R5F real-time processor running up to 450MHz
- Optional Front panel RS422/RS485 GPIO interface
- Optional 3×40/100G Optical Transceivers to VITA 66 Backplane Interface
- Multiple levels of hardware and software security
Next Generation “WILD Mezzanine Card HSS” (WMC-H) Site
- Optimized for JESD-based ADCs and DACs or Optical Transceivers
- For High Bandwidth Applications
- Annapolis Mezzanine products with “WH” prefix
- SOSA Aligned backplane I/O
- Optimized for VITA 66/67 interfaces
- Optimized for cooling
- Allows larger form factor cards for higher IO density
- Available options:
- WHDMF1: Jariet Electra-MA: 2TX (61.4GSps)/2RX (64.0GSps)
- WHGM65: AMD Xilinx RFSoC: 4TX (9.85GSps)/4RX (5.0GSps)
- WHQMB1: ADI Apollo MxFE: 4TX (28.0GSps)/4RX (20.0GSps)
- Others covered under NDA. Contact Factory for more information.
Mechanical and Environmental
- 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
- Supports OpenVPX payload profile:
- SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
- SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (no P2A connectivity)
- Available with 85°C ambient air temperature or card edge support and -55°C power-on
- Available with -65°C to 105°C storage temperature
- Air, Air-Flow-Through or Conduction Cooled
- Only requires +12V and +3.3VAUX from backplane
- Developed in alignment with the SOSA™ Technical Standard 1.0
- RT4 backplane connectors for up to 200G support
Application Development
- Full Board Support Package for fast and easy Application Development
- Includes source for all provided software components and examples on Versal PEs
- Open CoreFire™ Support
- Graphical RTL generation of algorithm blocks
- Feeds RTL development flow
- Boot methodology and development flow path options:
- Dynamic Function eXchange (DFX) via Abstract Shell Configuration
- RTL design of the Reconfigurable Module (RM)
- Design iteration speed up with reduced compile times
- CIPS stands while RM region can be reloaded
- Monolithic Configurations
- Traditional full RTL design
Ordering information
There are a number of different configurations available. Please request a quote via the orange button and we will help you align the spec to your requirements..
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