The 3.0 GSps 12-Bit ADC & DAC WFMC+ was designed from the ground up for latency-sensitive DRFM applications. The Board Support Interface, which is available in VHDL or CoreFire Next Application Design Suite, was also designed from the beginning to be suited for DRFM applications. This interface provides a Digital Bypass Mode to achieve the lowest possible latency and a Fabric Space Mode to allow the user to do additional processing and manipulation of the ADC data before returning it out the DAC. The Board Support Interface also includes a built-in Bypass Delay which can be controlled to be from 0 to 124 ADC sample clock periods. This allows the user to “walk” the latency out from the minimum Digital Bypass Mode latency to slightly beyond the Fabric Space Latency, providing for a smooth latency transition between the two modes.
The CoreFire Next Design Suite, Annapolis’ FPGA Design Tool, allows the user to design an ultra-low latency DRFM-optimized application in minutes.
The 3.0 GSps 12-Bit ADC & DAC WFMC+ is shipped with a custom heatsink which enables proper cooling of the ADC. An on-board temperature monitor is also supplied which allows for real-time monitoring of the ADC’s internal die temperature.
The 3.0 GSps 12-Bit ADC & DAC WFMC+  provides high fidelity and high speed analog-to-digital and digital-to-analog conversion along with a rugged design.
 

General

• One ADC and one DAC running at up to 3000MSps, each at 12-bits
• Ultra Low latency from ADC SMA input to DAC SMA output
• Digital Bypass Mode has built-in run-time adjustable delay providing additional delay from 0ns up to 124 Sample Clock periods, in increments of 4 periods
• Capability to have two ADC channels and two DAC channels in one 6UOpenVPX slot when plugged into WILDSTAR OpenVPX FPGA cards
• Compatible with any WILDSTAR mainboard with a WFMC+ slot
• Firmware and Software Board Support Interface provided in CoreFire Next and VHDL source

 
ADC and DAC Performance

• Sample Rate: 1GSps – 3GSps
• ADC and DAC Resolution: 12 bits

 
I/O Connectors

• Optional 50 SMA or VITA 67
• Six I/O Connectors
• One Analog Input
• One Analog Output
• One Differential Clock Input
• One Trigger Input
• One PLL Reference Input

 
Mechanical and Environmental

• Integrated Heatsink and EMI / Crosstalk Shields
• Commercial and Industrial Temperatures Available

 
Clock Synchronization

• Software-selectable external clock input or onboard PLL clock
• All ADCs and DACs across multiple mezzanine cards can be synchronized using WILDSTAR Clock Distribution Boards and select WILDSTAR Backplanes

There are a range of options available. Please contact Sarsen to discuss your project requirements.