Technical
Each card has two WILD FMC+ (WFMC+) next generation IO sites based on FMC/FMC+ specification.
While supporting standard FMC and FMC+ cards it also allows larger form factor Annapolis WFMC+ cards for higher IO density.
WFMC+ supports 32 HSS and 100 LVDS IO for higher density ADC and DAC solutions as well as stacking two IO cards per site.
Specifications
General Features
- Three Xilinx Kintex UltraScale™ XCKU115 or Virtex UltraScale+™ XCVU5P/XCVU9P FPGAs
- Up to 20,520 DSP Slices per board
- Up to 7,758,000 logic cells per board
- GTH transceivers operating up to 16.3 Gbps
- GTY transceivers operating up to 32.75 Gbps
- Hard 8x PCIe Gen3 endpoint for DMA and register access
- FPGAs programmable from attached flash or Annapolis provided software API
- 16 or 20-nm copper CMOS process
- DDR4 DRAM ports on all FPGAs running up to 2400 MT/s
- Two 80-bit ports per FPGA
- Up to 20 GB/FPGA, up to 60 GB/board
- Up to about 40 GB/s per FPGA
- ECC optional
- Xilinx Zynq UltraScale+™ MPSoC EG Motherboard Controller (XCZU9EG or XCZU15EG)
- Quad-core 64-bit ARM® Cortex-A53 running up to 1.3GHz
- Dual-core 32-bit Cortex-R5 real-time processor running up to 533 MHz
- Mali-400 MP2 graphics processing unit running up to 600 MHz
- 16nm FinFET+ programmable logic
- 4 GB 64-bit DDR4 memory running up to 1200 MHz for over 9 GB/s of potential bandwidth
- 4 or 32 GB SLC SATA SSD for filesystem
- Dedicated 2x PCIe Gen2 connection to PCIe switch, with ZYNQ+ selectable as root complex or endpoint
- 8 High Speed Serial Interfaces running up to 16Gbps from ZYNQ+ Fabric to other FPGAs
- Each 2x HSS link defaults to 128-bit AXI interface into ZYNQ+ CPU with IOPEs as master
- 2 High Speed Serial interface from FPGA fabric to backplane (CP2 and CP4) supporting 10.3 Gbps line rate
- Provides dedicated AXI bus to FPGA for register access without requiring PCIe interface
- USB 2.0/3.0 support to backplane or front panel USB-C connector
- RS 232/422/485 interface to backplane
- USB Uart console to front panel or backplane
- Board support enabling user customization of ZYNQ+ design
- Multiple levels of hardware and software security
- PLX PCI Express Gen3 Switch
- Allows expansion plane “chaining” of PCIe bus between adjacent slots. No dedicated PCIe switch slot needed.
OpenVPX Backplane I/O
- 24x High Speed Serial IO lanes to VPX Backplane (P1/P4) for 60 GB/s of Full Duplex Bandwidth
- Two PCIe Gen3 8x Connections to VPX Backplane (P2)
- 32 LVDS and 8 Single Ended lines to P5
- Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
- External clock and IRIG-B Support via Backplane
- 10/100/1000BASE-T support for Zynq+ with on-board magnetics
- Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK
- Allows points-to-point, very high quality backplane connections to payload cards
- Allows a system reference clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards without front panel connections needed
- Allows 1000s of analog channels across many backplanes/chassis to be synchronized via backplane
Front Panel I/O
- Two WILD FMC+ (WFMC+) next generation IO sites based on FMC+ specification
- Accepts standard FMC and FMC+ cards (complies to FMC+ specification)
- Allows larger form factor Annapolis cards for higher IO density
- Supports additional LVDS IO for higher density ADC and DAC solutions
- Supports stacking (2 IO cards per site) when at least one card is WFMC+
- Up to 32 High Speed Serial and 100 LVDS connections to FPGA
- Support for double wide cards
- Simultaneous Optics and ADC/DAC use with two slots
- Protocol Agnostic HSS connections support 10/40/100 Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocols
- SMA for clock in, clock out or IRIG-B in supporting multiple IO standards and terminations.
- Micro USB connector for CPU serial port (uses USB to UART bridge chip)
Application Development
- Open Project Builder Application Design Suite
- Full Board Support Package for Fast and Easy Application Development Computational, DSP and Data Flow Control Cores (FFTs, FIR, Math, etc)
- Develop in GUI environment or create VHDL and use HDL environment
- Built-in Debugger for Hardware in the loop Debugging
- Communication Cores Included (10/40Gb Ethernet and AnnapMicro Protocol cores)
- VHDL Model includes Source Code for Hardware Interfaces
- Supports High-Level Synthesis (HLS) Design Flow
- VHDL BSP packages including full synthesis and simulation support
- IOPE JTAG Access through RTM, Ethernet, or Zynq PCIe
- Board control and status monitoring can be local (stand-alone), remote (via Ethernet or PCIe) or hybrid (both local and remote)
System Management
- System Management using Intelligent Platform Management Interface (IPMI)
- Diagnostic monitoring and configuration
- Current, Voltage and Temperature Monitoring Sensors
- Hot Swappable (exclusive to WILDSTAR OpenVPX EcoSystem)
Mechanical and Environmental
- 6U OpenVPX (VITA 65) Compliant, 1” VITA 48.1 spacing
- Supports OpenVPX payload profile:MOD6-PAY-4F1Q2U2T-12.2.1-n
- Integrated Heat Sink and Board Stiffener
- Available in Extended Temperature Grades
- Air Cooled Only
- RTM available for additional I/O
Ordering information
There are a number of different configurations, please contact Sarsen Technology to discuss your application.