General Features
One Versal™ Premium VP2502 FPGA
7,392 DSP Slices and 3,737,720 logic cells
366 Mb of High Bandwidth, Low Latency UltraRAM
472 AI Engines
118 Mb AI Engine Data Memory
Five 32-bit LPDDR4 DRAM ports running up to 3700 MT/s
Dual-core 64-bit ARM® Cortex-A72 running up to 1.4GHz
Dual-core 32-bit Cortex-R5F real-time processor running up to 600MHz
Optional Front panel RS422/RS485 GPIO interface
Optional 2/3×40/100G Optical Transceivers to VITA 66 Backplane Interface
Multiple levels of hardware and software security
 
Next Generation “WILDSTAR Mezzanine Card HSS” (WMC-H) Site
Optimized for JESD-based ADCs and DACs or Optical Transceivers
For High Bandwidth Applications
Annapolis Mezzanine products with “WH” prefix
SOSA Aligned backplane I/O
Optimized for VITA 66/67 interfaces
Optimized for cooling
Allows larger form factor cards for higher IO density
Based on FMC+
Available options:
WHDMF1: Jariet Electra-MA: 2TX (64GSps)/2RX (64GSps)
Xilinx RFSoC: 2TX (5GSps)/8RX (5GSps)
Xilinx RFSoC: 4TX (5GSps)/4RX (5GSps)
Others covered under NDA. Contact Factory for more information.
 
Mechanical and Environmental
3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
Supports OpenVPX payload profile:
SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
Available with 85C ambient air temperature or card edge support and -55C power-on
Available with -65C to 105C storage temperature
Air, Air-Flow-Through or Conduction Cooled
Only requires +12V and +3.3VAUX from backplane
Developed in alignment with the SOSA™ Technical Standard 1.0
RT3 backplane connectors for 100G support
 
Application Development
Full Board Support Package for fast and easy Application Development
Includes source for all provided software components and examples on Versal PEs
Open CoreFire Next™ support
HDL generation
Three development flow paths:
Traditional RTL development flow
HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream
*NEW* Dynamic Function eXchange (DFX) RTL development flow
Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
Design refactors and testing iterations significantly sped up
CIPs function remains active while fabric is reloaded
*NEW* Vitis™ Platform Project development flow

These SOSA-aligned Plug-In Cards (PIC) include one Versal Premium VP2502 FPGA with AI Engines. AMD’s new Versal Premium Adaptive Compute Accelerated Platform (ACAP) with AI Engines are engineered for high-performance signal processing applications like radar, electronic warfare, and signal intelligence applications. In addition to being able to run AI models more efficiently, the addition of the AI engines allows the signal processing workloads to be split between the DSP and AI engines, using each most efficiently for the relative tasks, with improved overall performance.
 
The 3XV5 also has superior connectivity. It offers an optional front panel RS422/RS485 GPIO interface and 2/3×40/100G Optical Transceivers to VITA 66 backplane interface.
 
Additional flexibility is built into a high bandwidth next-generation mezzanine site that is optimized for JESD-based ADCs and DACs or optical transceivers.

There are a range of options available. Please contact Sarsen to discuss your project requirements.