General Features
One Versal™ Premium VP1502/VP1702 FPGA
Up to 10,896 DSP Slices and 5,557,720 logic cells
Up to 541 Mb of High Bandwidth, Low Latency UltraRAM
Five 32-bit LPDDR4 DRAM ports running up to 3700 MT/s
Dual-core 64-bit ARM® Cortex-A72 running up to 1.4GHz
Dual-core 32-bit Cortex-R5F real-time processor running up to 600MHz
Optional Front panel RS422/RS485 GPIO interface
Optional 6x100G Optical Transceivers to VITA 66 Backplane Interface
Multiple levels of hardware and software security
 
Mechanical and Environmental
3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
Supports OpenVPX payload profile:
SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n (SOSA Primary)
SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (SOSA Secondary)
Available with 85°C ambient air temperature or card edge support and -55°C power-on
Available with -65°C to 105°C storage temperature
Air, Air-Flow-Through or Conduction Cooled
Only requires +12V and +3.3VAUX from backplane
Developed in alignment with the SOSA™ Technical Standard 1.0
RT3 backplane connectors for 100G support
 
Application Development
Full Board Support Package for fast and easy Application Development
Includes source for all provided software components and examples on Versal PEs
Open CoreFire Next™ support
HDL generation
Three development flow paths:
Traditional RTL development flow
HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream
*NEW* Dynamic Function eXchange (DFX) RTL development flow
Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
Design refactors and testing iterations significantly sped up
CIPs function remains active while fabric is reloaded
*NEW* Vitis™ Platform Project development flow

These SOSA-aligned Plug-In Cards (PIC) include one Versal Premium VP1502/VP1702 FPGA and have five 32-bit LPDDR4 DRAM ports running up to 3700 MT/s.
 
There is also an on-board dual-core ARM CPU running up to 1.4 GHz which can be used for local application requirements.  It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs.  It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.
 
The air-cooled 3XV7 is hot swappable, allowing for more system reliability. This feature is unique to Annapolis and was developed because our experience with OpenVPX systems has shown it invaluable, so a whole chassis does not need to be shutdown to remove a single board.
 

There are a range of options available. Please contact Sarsen to discuss your project requirements.