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WWLCK2


Overview

KSII DSP WFMC+

The KSII DSP WFMC+ - WWLCK2 from Annapolis Micro Systems provides high-performance digital signal processing along with a rugged design.

Based on the Texas Instruments 66AK2H14 KeyStone II ARM/DSP, the KSII DSP WFMC+ is shipped with a custom heatsink which enables proper cooling of the DSP. On-board temperature monitors are also supplied which allows for real-time monitoring.

Compatible with any WILDSTAR mainboard with a WFMC+ slot.

Technical

The KSII DSP WFMC+ provides high-performance digital signal processing along with a rugged design. The KSII DSP WFMC+ is shipped with a custom heatsink which enables proper cooling of the DSP. On-board temperature monitors are also supplied which allows for real-time monitoring.
 

Specifications

One Texas Instruments 66AK2H14 KeyStone II ARM/DSP
  • CorePac Processors:
Quad Cortex-A15 processors running at 1400 MHz
Eight C66x DSP Cores running at 1200 MHz
  • One 4GB 72-bit DDR3 DRAM port
  • 5 Gbps x4 Serial Rapid IO V2.1 interface to Motherboard FPGA
  • Up to 6.25 Gbps x4 HyperLink interface to Motherboard FPGA
  • 1Gb Ethernet Interface to VPX backplane
  • 1Gb Ethernet Interface to ZYNQ Motherboard Controller (MC)
  • Front Panel USB UART
  • Optional JTAG Debug Connector
  • Choice of 66AK2H14 Rev B DSP devices, to support different lead times:
66AK2H14BXAAW24: Commercial temp, with security accelerator
66AK2H14BAAWA24: Industrial temp, NO security accelerator
66AK2H14BXAAWA24: Industrial temp, with security accelerator
66AK2H14BSAAWA24: Industrial temp, with security accelerator, with high security device with production keys
 
Hardware Coprocessors
  • Four Turbo Decoders
  • Supports WCDMA/HSPA/HSPA+/TDSCDMA,LTE, LTE-A, and WiMAX
Eight Viterbi Decoders
Four WCDMA Receive Acceleration Coprocessors
WCDMA Transmit Acceleration Coprocessor
Six Fast Fourier Transform (FFT) Coprocessors
Bit Rate Coprocessor
WCDMA/HSPA+, TD-SCDMA, LTE, LTE-A, and WiMAX Uplink and Downlink Bit Processing
  • Sixteen Rake/Search Accelerators (RSA) for
Chip Rate Processing for WCDMA Rel’99, HSDPA, and HSDPA+
Reed-Muller Decoding
  • Pluggable module can be swapped out or upgraded as needed to match future design constraints
Pluggable module reduces the risk of development
  • General control of the TI DSP module will be via I2C from the ZYNQ baseboard controller (i.e. reset, power enable, status etc)

Ordering information

There are a range of options available. Please contact Sarsen to discuss your project requirements.