Technical
WABEC0 is compatible with W16D31 Backplane.
See WABEC1 for a passive SCLK distribution up to 250 MHz, and fewer secondary AUXCLK and REFCLK copies.
Specifications
Sample Clock Outputs
REFCLK (Typically 10-100MHz)
- 11 primary differential radial REFCLK outputs
- 3 secondary differential radial REFCLK outputs
AUXCLK (Typically 1PPS)
- 11 primary differential radial AUXCLK outputs
- 3 secondary differential radial AUXCLK outputs
Environmental
- Runs from backplane 12V
- Standard: -40 to 85°C Operating & Storage
- Available: -55 to 85°C Operating & -65 to 105°C Storage
- Selectable Outputs controlled from the local WABGM0 Chassis Manager via I2C or onboard jumpers.
- Does not cover any VITA 66/67 openings, allowing for full support
Ordering information
There are a range of options available. Please contact Sarsen to discuss your project requirements.
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