These SOSA-aligned Plug-In Cards (PIC) include one Versal Premium VP1702 FPGA and have five 32-bit LPDDR4 DRAM ports running up to 3700 MT/s.
If front panel and/or backplane IO is required, Annapolis offers extraordinary density, bandwidth and analog conversion choices. Each card has a next generation mezzanine site that is optimized for JESD-based ADCs and DACs. Based on FMC/FMC+ specification, it allows larger form factor cards for higher IO density. VITA 66/67 optical/RF backplane support is included.
There is also an on-board dual-core ARM CPU running up to 1.4 GHz which can be used for local application requirements. It is accessible over backplane PCIe or Ethernet and provides dedicated AXI interfaces to all FPGAs. It is also used to query board health like FPGA temperature and power. It is connected to the OpenVPX control plane via 1GbE.
General Features
• One Versal™ Premium VP1702 FPGA
o Up to 10,896 DSP Slices and 5,557,720 logic cells
o Up to 541 Mb of High Bandwidth, Low Latency UltraRAM
o Five 32-bit LPDDR4 DRAM ports running up to 3700 MT/s
o Dual-core 64-bit ARM® Cortex-A72 running up to 1.4GHz
o Dual-core 32-bit Cortex-R5F real-time processor running up to 600MHz
• Optional Front panel RS422/RS485 GPIO interface
• Optional 2/3×40/100G Optical Transceivers to VITA 66 Backplane Interface
• Multiple levels of hardware and software security
Next Generation “WILD Mezzanine Card HSS” (WMC-H) Site
• Optimized for JESD-based ADCs and DACs or Optical Transceivers
o For High Bandwidth Applications
o Annapolis Mezzanine products with “WH” prefix
• SOSA Aligned backplane I/O
• Optimized for VITA 66/67 interfaces
• Optimized for cooling
• Allows larger form factor cards for higher IO density
• Based on FMC+
• Available options:
o WHDMF1: Jariet Electra-MA: 2TX (64GSps)/2RX (64GSps)
o Xilinx RFSoC: 2TX (5GSps)/8RX (5GSps)
o Xilinx RFSoC: 4TX (5GSps)/4RX (5GSps)
o ADI Apollo MxFE 4TX (28 GSps)/4 RX (20 GSps)
o Others covered under NDA. Contact Factory for more information.
Mechanical and Environmental
• 3U OpenVPX (VITA 65) Compliant, 1” VITA 48.2 spacing
• Supports OpenVPX payload profile:
o SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
o SLT3-PAY-1F1U1S1S1U1U4F1J-14.6.13-n (no P2A connectivity)
• Available with 85°C ambient air temperature or card edge support and -55°C power-on
• Available with -65°C to 105°C storage temperature
• Air, Air-Flow-Through or Conduction Cooled
• Only requires +12V and +3.3VAUX from backplane
• Developed in alignment with the SOSA™ Technical Standard 1.0
• RT3 backplane connectors for 100G support
Application Development
• Full Board Support Package for fast and easy Application Development
• Includes source for all provided software components and examples on Versal PEs
• Open CoreFire Next™ support
o HDL generation
• Three development flow paths:
- Traditional RTL development flow
HDL/IPI -> Vivado™ -> PetaLinux project -> Bitstream
- *NEW* Dynamic Function eXchange (DFX) RTL development flow
- Includes abstract shell approach which avoids PetaLinux rebuilds on iterations
- Design refactors and testing iterations significantly sped up
- CIPs function remains active while fabric is reloaded
- *NEW* Vitis™ Platform Project development flow
The WS3XV1 is highly configurable. Please request a quote and one of our team will be in touch to discuss your application requirements.