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WC3170 7-Slot 3U OpenVPX SOSA-Aligned Chassis


7 Slot 3U OpenVPX 100GbE SOSA-Aligned Chassis

The WC3170 from Annapolis Micro Systems is a 7 slot 3U OpenVPX SOSA-aligned chassis.

This is a COTS 3U VPX 100GbE chassis and backplane combination that has been specifically designed to economically speed the development of SOSA-aligned 100Gb Ethernet boards and systems.

The WC3170 100GbE SOSA-aligned chassis includes a chassis, backplane, and secure chassis manager. The 7-slot air-cooled chassis and backplane incorporates slots for up to four conduction-cooled 3U VPX Payload Boards, plus a 100GbE Switch, SBC, and VITA 62 power supply, delivering up to 700W. Optional FPGA boards, 100GbE switch, storage, SBC, VITA blocks and cables are also available.

The Chassis Manager is VITA 46.11/SOSA-aligned and utilises a Xilinx UltraScale+ ZU5EG MPSoC.

The WC3170 SOSA-aligned chassis is VITA 65 compliant and designed and built in the USA.


Chassis and Backplane

  • SOSA-aligned
  • Front-loading, air-cooled Chassis with conduction-cooled slots
  • 7 3U OpenVPX Slots
    • 4 Payload Slots
    • 1 SBC Slot
    • 1 40/100GbE Switch Slot
    • 1 VITA 62 Power Supply Slot – Standard or 12V-Heavy
  • Input power is 28VDC per MIL-STD-704F
  • 25 Gbps Line Rates on Data and Expansion Planes
    • 25/40/100Gb Ethernet
    • SDR/DDR/QDR/EDR Infiniband
    • Gen 3/4 PCI Express
    • Custom protocols up to 25Gbps per lane
  • SOSA-aligned Backplane profiles
    • Payload Profile: SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
    • Payload Profile: SLT3-PAY-1F1F2U1TU1T1U1T-14.2.16
    • Switch Profile: SLT3-SWH-6F1U7U-14.4.14
  • VITA 66.5C and VITA 67.3C for payload slots
  • Integrated ultra-low skew AUXCLK/REFCLK radial distribution
  • Chassis manager connector handles JTAG, maintenance ports (UARTs) and control
  • Up to 4 MIL-DTL-38999 SOSA-aligned circular connectors with 19 RF connections – one for each payload slot
  • LED Status Indicators

Chassis Manager

  • SOSA-aligned and VITA 46.11 compliant
  • Xilinx UltraScale+ ZU5EG MPSoC running Linux for CHmC
    • Processing Subsystem (PS)
      • Quad core A53 ARM running at 1.2 GHz
      • Dual core R5 ARM
      • 4GB DDR4 DRAM
      • 128MB QSPI NOR
    • Programmable Logic subsystem (PL)
      • 256K System Logic cells in Programmable Logic
      • 18Mb of UltraRAM
      • 128MB QSPI NOR
      • Dual 128KB battery backed NV SRAM
  • Integrated JTAG access/control from chassis manager to each slot
    • External JTAG connection with SW selectable multiplexing from each slot
    • Xilinx JTAG over ethernet via Chassis Manager

Application Development

  • Standard Chassis Manager support delivered with all systems
    • IPMI Chassis Manager support with redundant IPMB
      • VITA 46.11 conformant and SOSA-aligned
      • Tier 2 Chassis Manager supporting Tier 1 and Tier 2
    • Chassis voltage and temperature sensor monitoring
    • Fan control and monitoring
    • UART support to payload cards
    • JTAG support to payload cards
  • Optional Full Board Support Package for Chassis Manager
    • Enables customisation if needed of Zynq PS, PL
    • Provides fast and robust HDL-based application development environment

Technical documents

Ordering information

There are a number of configurations available. Please contact Sarsen to discuss your application requirements.


Associated products