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High-Density 13 Slot 3U OpenVPX 100GbE SOSA-Aligned 19" Rackmount Chassis

The WC31DH WILD100 13-Slot 3U OpenVPX Chassis from Annapolis Micro Systems includes a 100Gb Ethernet-enabled COTS rackmount 3U VPX Chassis, Backplane, and Chassis Manager. It is a higher density version of the WILD100 14-Slot 3U OpenVPX Chassis (WC31E0).

The WC31DH Chassis incorporates slots for up to eight conduction-cooled 3U VPX Payload Boards, two HD Switches, a Radial Clock, and two VITA 62 power supplies.

It includes two HD Switch slots that feature high-density VITA 91 connectors with double the available density, up to 64 lanes of Ethernet or PCIe or 128 LVDS pairs. VITA 91 high-density connectors allow for a completely switched backplane. This supports all the slots being on the same non-blocking Ethernet switch instead of two switches chained together, and it facilitates a flexible, programmable expansion plane. This supports either 8x or 4x Gen4 PCIe, plus eight LVDS or dual 100Gb Ethernet. The two HD switch slots allow the WC31DH Chassis to handle all Data and Control Plane Ethernet via one slot, with the second switch slot dedicated to the expansion plane – Ethernet, PCIe and/or LVDS (for low latency jamming or radar applications).

The Chassis Manager is VITA 46.11/SOSA-aligned and utilizes a Xilinx UltraScale+ ZU5EG MPSoC. It is plugged directly onto rear of backplane, or is cabled.


Chassis and Backplane Features

  • Front-loading, air-cooled Chassis with conduction-cooled slots
  • Thirteen 3U OpenVPX Slots
    • Eight 14.6.11 Primary RF/Compute Intensive profile
    • Two HD Switch profiles
    • One 14.9.2 Timing profile
    • Two 12V-only VITA 62 Power Supply Slots
  • Input power is 28VDC per MIL-STD-704F
  • 25 Gbps Line Rates on Data and Expansion Planes
    • 25/40/100Gb Ethernet
    • SDR/DDR/QDR/EDR Infiniband
    • Gen 3/4 PCI Express
    • Custom protocols up to 25Gbps per lane
  • SOSA-aligned Backplane profiles
    • Payload Profile: SLT3-PAY-1F1U1S1S1U1U2F1H-14.6.11-n
    • Timing Profile: SLT3x-TIM-2S1U22S1U2U1H-14.9.2
  • VITA 66.5C and VITA 67.3C for payload slots
  • Integrated ultra-low skew AUXCLK/REFCLK radial distribution
  • WABGM0 Chassis manager connector handles JTAG, maintenance ports (UARTs) and control
  • Support for CLK1 direct connection between payload slots (1,2,3,4,8,9,10,11) to Chassis Manager FPGA
  • LED Status Indicators

WABGM0 Chassis Manager

  • SOSA-aligned and VITA 46.11 compliant
  • Plugged directly onto backplane, or cabled
  • Xilinx UltraScale+ ZU5EG MPSoC running Linux for CHmC
    • Processing Subsystem (PS)
      • Quad core A53 ARM running at 1.2 GHz
      • Dual core R5 ARM
      • 4GB DDR4 DRAM
      • 128MB QSPI NOR
    • Programmable Logic subsystem (PL)
      • 256K System Logic cells in Programmable Logic
      • 18Mb of UltraRAM
      • 128MB QSPI NOR
      • Dual 128KB battery backed NV SRAM
  • Integrated JTAG access/control from chassis manager to each slot
    • External JTAG connection with SW selectable multiplexing from each slot
    • Xilinx JTAG over ethernet via Chassis Manager
  • Optional MIL-STD-1553 support
  • Optional advanced security features

Application Development

  • Standard Chassis Manager support delivered with all systems
    • IPMI Chassis Manager support with redundant IPMB
      • VITA 46.11 conformant and SOSA-aligned
      • Tier 2 Chassis Manager supporting Tier 1 and Tier 2 with Tier 3 in process
    • Chassis voltage and temperature sensor monitoring
    • Fan control and monitoring
    • UART support to payload cards
    • JTAG support to payload cards
  • Optional Full Board Support Package for Chassis Manager
    • Enables customization if needed of Zynq PS, PL
    • Provides fast and robust HDL-based application development environment

Ordering information

There are a number of configurations available. Please contact Sarsen to discuss your application requirements.


Associated products